Japanese Patent Laid-open No. 2002-368143 (Patent Literature 1) discloses a non-volatile semiconductor memory device including a plurality of memory cells arranged in a matrix of rows and columns. In the non-volatile semiconductor memory device disclosed in Patent Literature 1, the memory cells arranged in the matrix each include a memory transistor including a charge storage layer made of a nitride film or polysilicon, and a bipolar switch transistor. This non-volatile semiconductor memory device includes, for example, a plurality of EEPROM word lines EEWL extending in the row direction and a plurality of data lines DL and source lines SL extending in the column direction. Memory cells are provided at intersections between the EEPROM word lines EEWL in the row direction and the data lines DL and the source lines SL in the column direction.
The switch transistor of each memory cell has a base connected with the source of the memory transistor. The memory transistor has a gate connected with one of the EEPROM word lines EEWL, and a drain connected with one of the data lines DL to receive voltage from the EEPROM word line EEWL and the data line DL. The switch transistor has an emitter connected with one of the source lines SL, and a collector provided as a well of the memory transistor.
When data is to be programmed into a memory cell in the non-volatile semiconductor memory device, voltage is applied to the EEPROM word line EEWL, the data line DL, and the source line SL connected with the memory cell so that charge is injected into the charge storage layer through the source of the memory transistor by a voltage difference between the gate and source of the memory transistor of the memory cell, thereby achieving a data programmed state.